M.Tech student in VLSI & Embedded Systems with hands-on experience in RTL, FPGA, and PLC systems. I build efficient hardware solutions and focus on validation, optimization, and system-level design.
VLSI
RTL Design, CMOS, Digital Circuits
Tools
Verilog, VHDL, Vivado
Programming
Python, C, Data Analysis
Embedded
Embedded Systems, PLC
Concepts
Signal Processing, ML Basics
Overview: Studied impact of transistor sizing (W/L) on CMOS gate delay.
Tools: Python, NumPy, Pandas, Matplotlib
Work: Cleaned simulation data, plotted delay vs W/L, built regression model.
Concepts: CMOS delay, curve fitting, trade-offs (speed vs power).
Result: Identified optimal sizing trend to minimize delay.
Overview: 4-bit priority encoder designed in Verilog.
Tools: Verilog, Xilinx Vivado, ZedBoard (Zynq-7000)
Work: RTL coding, testbench simulation, synthesis, on-board validation.
Concepts: Combinational logic, RTL design, timing checks.
Result: Correct priority output verified on FPGA hardware.
Overview: Enhanced low-quality CCTV images using MSVD.
Tools: Python, OpenCV, NumPy
Work: Applied MSVD decomposition, filtering, contrast enhancement.
Concepts: Signal processing, noise reduction, image enhancement.
Result: Improved clarity and visibility for analysis.
Role: PLC Control Panel Intern
Work: Panel wiring, I/O signal interfacing, debugging faults.
Tools: PLC modules, relays, sensors, wiring diagrams
Concepts: Industrial automation, real-time control systems
Impact: Reduced troubleshooting time by systematic signal validation.
Role: Electronics Intern
Work: Observed PCB assembly, testing, validation processes.
Tools: Testing rigs, inspection tools, documentation
Concepts: Traction electronics, system integration
Impact: Gained understanding of large-scale manufacturing workflows.
anuraagnandan2003@gmail.com
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